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Orcad Capture: DRC reports port mismatch error in Xilinx design
Keywords: DRC, port, mismatch, Orcad, Capture
General Description: When running Capture's Design Rules Check
on a Xilinx design, a user may get a port mismatch error.
Some Xilinx models in the Orcad library have ports that are
incorrectly labeled. You must relabel these ports.
To do so, descend into the part and change the hierarchical
port type from output to 3-state.
The models with mislabeled ports are:
BUFE, BUFE4, BUFE8, BUFE16, BUFT4, BUFT8, BUFT16, OBUFE, OBUFE4,
OBUFE8, OBUFE16, OBUFT4, OBUFT8, and OBUFT16.