AR# 41608


MIG v3.7 Virtex-6 DDR3 - "app_wdf_wren" stays low even though the write data FIFO should be ready


During simulation I see "app_wdf_wren" staying low for some period of time. Why does this occurwhen the write data FIFO should be ready to receive data?


Sometimes, this occurs when the "occ_cnt" value counts incorrectly in "ui_wr_data.vhd."

VHDL Users

Change the following line in "ui_wr_data.vhd" from:

wr_data_end <= app_wdf_end_r1 AND app_wdf_rdy_r_copy1;

to include "app_wdf_wren_r1":

wr_data_end <= app_wdf_end_r1 AND app_wdf_rdy_r_copy1 AND app_wdf_wren_r1;

Verilog Users

Change the following line from:

wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1;


wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;

The "wr_data_end" indirectly affects the "occ_cnt" value, which in turn affects the wr_data_index and wr_data_addr and can cause problems in hardware and simulations.

This is fixed in the ISE 13.2 MIG v3.8 release.



Answer Number 问答标题 问题版本 已解决问题的版本
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 41608
日期 05/20/2012
状态 Active
Type 已知问题
器件 More Less
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