We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4161

12.1 Timing - I cannot create a TIMESPEC that includes the TDO/MD1 pin on FPGA architectures


I cannot create TIMESPECs that include the TDO/MD1 output pad on Xilinx FPGAs. When I apply time constraints that directly feed the TDO pin, the timing report indicates the following: 

"0 items analyzed, 0 timing errors detected."


You can trace the delay to the IOB pin, but you cannot determine the delay in the IOB. This can be done in Timing Analyzer by using the path filters to select the appropriate source and destination. (The destination is the net driving the buffer connected to the TDO.)
AR# 4161
日期 05/14/2014
状态 Archive
Type 已知问题