AR# 4166


V1.5 CORE Generator - What's new in the v1.5 release?


Keywords: CORE Generator, COREGEN, Coregen, v1.5

Urgency: Standard

General Description:
What's new in the v1.5.0 release?


- HP-UX 10.2 support
- EDIF is generated for implementation instead of XNF;
- Verilog behavioral models
- characterization data (CLB utilization and speed) have been
added to CORE Generator module datasheets
- limited Virtex architecture support has been
added (dual and single port block RAM modules)
AR# 4166
日期 02/11/2001
状态 Archive
Type 综合文章
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