General Description:
Sample .COE files for Virtex block RAM can be found in the directory
$XILINX/coregen/data
Single Port Block RAM .coe file
-------------------------------
---- Clip here ----
component_name=myspbram;
Depth = 256;
Data_Width = 32;
Radix = 16;
Default_Data = FFF;
MEMORY_INITIALIZATION_VECTOR = FF0,F0F,0FF,FF4,F4F,4FF,FF8,F8F,8FF;
Dual Port Block RAM .coe file
-----------------------------
---- Clip here ----
component_name=mydpbram;
Depth_A = 4096;
Data_Width_A = 16;
Depth_B = 1024;
Data_Width_B = 64;
Radix = 2;
Default_Data = 10101010;
MEMORY_INITIALIZATION_VECTOR=
1111111111111110,
1111111111111101,
1111111111111011,
1111111111110111;
AR# 4191 | |
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日期 | 05/13/2010 |
状态 | Archive |
Type | 综合文章 |