解决方案
General LogiCORE IP Video Deinterlacer Issues
LogiCORE IP Video Deinterlacer v3.00.a
There is a v3.00.a Rev1 patch available in (Xilinx Answer 61834). This patch is intended to fix issues listed below such as in (Xilinx Answer 61833).
- Initial release in ISE Design Suite 14.3, Vivado Design Suite 2012.3
Supported Devices (ISE)
- All Kintex-7 devices
- All Virtex-6 devices
- All Spartan-6 devices
New Features - ISE 14.1 design tools support
- Vivado 2012.3 design tools support
- AXI4LITE interface always enabled. GPP interface was removed.
- Port enablement for video stream interface (AXI-S or XSVI)
- Port enablement for memory interface (when C_MOTION=1)
Bug Fixes
Known Issues (ISE)
- (Xilinx Answer 50586) Why do I always get zeros back when reading from the Video Deinterlacer registers?
- (Xilinx Answer 59127) The Pulldown 2:2 Field mode selection description is reversed
- (Xilinx Answer 59461) Why does the Video Deinterlacer sometimes hang when the video input is interrupted?
- (Xilinx Answer 59848) Does the Video Deinterlacer support odd integers for the frame height?
- (Xilinx Answer 59850) Does the Video Deinterlacer expect an Start of Frame (SOF) for each field or each frame?
- (Xilinx Answer 60171) Why does changing the base and high address in the configuration GUI have no affect on the Video Deinterlacer core?
- (Xilinx Answer 61833) Why does the Accept Video bit in the Control Register always readback as '0'?
Known Issues (Vivado)
- (Xilinx Answer 50586) Why do I always get zeros back when reading from the Video Deinterlacer registers?
- (Xilinx Answer 52294) Why does the video Deinterlacer give incorrect results in Vivado 2012.3 when the XSVI interface is selected?
- (Xilinx Answer 56277) Why does the s_axis_video_tready signal behavior appear incorrect for the first input frame?
- (Xilinx Answer 59127) The Pulldown 2:2 Field mode selection description is reversed
- (Xilinx Answer 59461) Why does the Video Deinterlacer sometimes hang when the video input is interrupted?
- (Xilinx Answer 59848) Does the Video Deinterlacer support odd integers for the frame height?
- (Xilinx Answer 59850) Does the Video Deinterlacer expect an Start of Frame (SOF) for each field or each frame?
- (Xilinx Answer 60171) Why does changing the base and high address in the configuration GUI have no affect on the Video Deinterlacer core?
- (Xilinx Answer 61833) Why does the Accept Video bit in the Control Register always readback as '0'?
LogiCORE IP Video Deinterlacer v2.00.a
There is a v2.0 Rev2 patch available in (Xilinx Answer 50586). This patch is intended to fix issues listed below as (Xilinx Answer 50586).
- Initial Release in ISE Design Suite 14.1
Supported Devices (ISE)
- All Kintex-7 devices
- All Virtex-6 devices
- All Spartan-6 devices
New Features - ISE 14.1 software support
- Kintex-7 device support
Bug Fixes
Known Issues
LogiCORE IP Video Deinterlacer v1.0
There is a v1.0 Rev2 patch available in (Xilinx Answer 46986). This patch is intended to fix issues listed below as (Xilinx Answer 46232), (Xilinx Answer 46987) and (Xilinx Answer 47162).
- Initial release in ISE Design Suite 13.3 (with CORE Generator tool support)
Supported Devices
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA LX/LXT
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Spartan-6 -1L XQ LX
New Features:
- Initial release (with CORE Generator software support)
Bug Fixes:
Known Issues:
- (Xilinx Answer 45634) How do I generate a simulation model for the VideoDeInterlacer?
- (Xilinx Answer 46232) Does the Video Deinterlacer support Virtex-5 FPGA?
- (Xilinx Answer 46233) Why do I see a mismatch between documentation and the example test bench when preforming VFBC writes?
- (Xilinx Answer 46234) Why do I receive a FATAL error when I attempt to simulate the example test bench with the MPMC-VFBC interface selected?
- (Xilinx Answer 46341) Why do I receive an error when I attempt to use the XCO file in my ISE Project?
- (Xilinx Answer 46987) Why does the Video Deinterlacer pcore fail with an "NdgBuild:604 error" when I implement my XPS or ISE project?
- (Xilinx Answer 47162) Why do I get EDK:1596 Error when opening the my XPS project containing the Video Deinterlacer v1.00.a pcore?
- (Xilinx Answer 47227) Are all 32 bits in Tables 2-11, 2-12, and 2-13 used, or are some of them reserved?
- (Xilinx Answer 50771) I cannot generate a core with 10-bit or 12-bit color depth