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AR# 4200

FPGA Express 2.x, 3.x: Constraints Editor will not allow assignment of more than 4 BUFGs


Keywords: Express, clock buffers, BUFG, constraints editor

Urgency: Standard

When using Express 2.x to target an XC4000 series or Spartan device, the
Express Constraints Editor will not allow the assignment of more than four
global clock buffers to signals. The devices will allow up to eight clock
buffers to be used.


The solution is to instantiate all the desired clock buffers in your HDL code.

See (Xilinx Solution 3980) for examples in VHDL.
See (Xilinx Solution 3999) for examples in Verilog.
AR# 4200
日期 08/11/2003
状态 Archive
Type 综合文章