AR# 42152


PlanAhead - Retiming, register_duplication, and equivalent_register_removal options have no effect for 7 Series FPGA designs using global_opt


In the PlanAhead 13.2 and later software, I am able to see and set the following Map, Design Run Settings. However, they do not seem to take effect:


Are the options being used correctly?

Should these options be available for Artix-7, Kintex-7 and Virtex-7 FPGA designs?


The global_opt functionality, including -register_duplication (in conjunction with -global_opt) -retiming and
-equivalent_register_removal, was removed from the PlanAhead toolin ISE Design Suite 13.1 for Xilinx 7 series FPGA designs. However, these options incorrectly remain selectable in the the PlanAhead 13.2 and later software.

The options can be selected by the user, but they will not appear in the map command line.Therefore, they do not affect design implementation.

AR# 42152
日期 05/16/2012
状态 Archive
Type 已知问题
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