AR# 4219: 9.1i BitGen - Why does Virtex not pass data to DOUT? What is the purpose of the "-g DebugBitstream" option? How does a "debug bitstream" differ from a normal bitstream?
9.1i BitGen - Why does Virtex not pass data to DOUT? What is the purpose of the "-g DebugBitstream" option? How does a "debug bitstream" differ from a normal bitstream?
Keywords: bit stream, LOUT
What is the purpose of the BitGen "DebugBitstream" option (see below)?
-g DebugBitstream:Yes or -g DebugBitstream:No
What is the difference between a "regular" and a "debug" bitstream? Why would a device not pass data to DOUT?
A different bit file is created when DebugBistream is set to "Yes." This bit file contains more information and commands for debugging a serial download.
NOTE: You cannot use the "debug" bitstream for JTAG or SelectMAP downloads since these modes cannot process the LOUT command.
A debug bitstream includes the following commands that assist you in debugging configuration problems: - A LOUT write is included after the synchronization word (Header = 0x30010001, Data = 0x00000000) - Each frame is written individually (as opposed to the multiple frame write in a standard bitstream) - A LOUT write occurs after each frame (Header = 0x30010001, Data = frame address) - An explicit CRC check occurs after each frame (Virtex/-E/Spartan-II/-E only)
A LOUT write passes data to the DOUT pin. If the device is receiving commands correctly (i.e., the device is properly synchronized), the frame address of each frame will appear on the DOUT pin after the frame is written (the frame address is not a contiguous count -- it is a combination of the block type, major address, and minor address.) The equations for calculating the frame address for Virtex/-E/Spartan-II/-E devices are included in the Xilinx Application Note (Xilinx XAPP151): "Virtex Series Configuration Architecture User Guide". This information is not currently available for Virtex-II devices.
If a configuration bit is missed or added, or a clock glitch occurs, configuration commands no longer appear on proper 32-bit boundaries. Consequently, output of data on the DOUT pin stops. Each LOUT write is 32 bits.
A CRC check provides an error detection mechanism. If a "1" is changed to a "0," or vice-versa, the CRC check fails, the INIT pin goes Low, and configuration stops.
CRC Check - Virtex
A standard Virtex bitstream includes only one CRC check, which occurs at the end of the configuration sequence. If a bit is missed for some reason, the 32-bit alignment of the configuration data is lost, and the CRC check never occurs. In this scenario, the INIT pin never goes Low, even though the configuration data was not correctly received.
By writing each frame individually and adding a CRC check to each frame, the DebugBitstream option helps you pinpoint the place where a configuration data error might occur.
CRC Check - Virtex-II
A standard Virtex-II bitstream provides a CRC check for every frame write (Xilinx Answer 13790), so the DebugBitstream option does not provide additional CRC checks for Virtex-II devices.
Bitstream Size Considerations
Because many extra commands are added to the bitstream when the DebugBitstream option is specified, it is approximately 20% larger. This can cause the bitstream to be too large to fit into a PROM that can handle a standard bitstream. If the debug bitstream is prohibitively large, refer to (Xilinx Answer 7819) for information on manually adding LOUT writes to the bitstream.
Virtex configuration data is completely different from previous Xilinx families; it does not have the header, preamble, or length count information at the beginning of the bitstream. Additionally, the Virtex family does not "overflow" and pass configuration data out of the DOUT register as with previous FPGA families. Instead, the only way to pass data out through DOUT is by writing to the LOUT register. LOUT is a Legacy Data Out register that pipelines data to the DOUT pin.
Whenever a Virtex device is the only device in a configuration chain, no data is passed out of DOUT or written to the LOUT register. Whenever a Virtex device is in a configuration chain, it is necessary to pass data out of DOUT to configure a complete chain of devices. If you use the PROM File Formatter (or PROMGen) to concatenate bitstreams into a PROM file, the required writes to the LOUT register are handled automatically.
If you need to make manual modifications, Xilinx recommends modifying the .rbt file.
To modify the .rbt file, insert the extra data where needed, and update the "Bits:" field in the header. PROMGen uses this information to create a file of the proper length.