(On the PDA FIR filter, the input data width is limited to 24.)
解决方案
The limitations on the input data width for these particular modules are associated with the fact that the input coefficient values are represented with VHDL integer data types. VHDL integer data types are 32-bit data types by definition, and using 32-bit data types as inputs in these applications may cause arithmetic overflow problems on the outputs during behavioral simulation.