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AR# 42454

Spartan-6 FPGA Integrated Block for PCI Express - CORE Generator GUI shows a value of 0 for bit 15 of the Device Capabilities Register

描述

Version Found: v2.1

Version Resolved and other Known Issues: See (Xilinx Answer 45702).

The CORE Generator GUI shows that the Role-Based Error reporting bit or bit 15 of the Device Capabilities Register is set to 0.

However, if this bit is read back from the core it is set.

解决方案

The CORE Generator display value is incorrect and this bit is actually set to 1.



Note: "Version Found" refers to the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
42569 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.3 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
45702 Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions N/A N/A
AR# 42454
日期 09/22/2014
状态 Active
Type 综合文章
器件
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 13.2
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
的页面