AR# 42475

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13.1 PlanAhead - DIFF_HSTL_I_DCI outputs missing rule/data to catch illegal placement in HR bank

描述

Why are DIFF_HSTL_I_DCI outputs in 7 series FPGAs not getting a DRC error when assigned in an HR bank?

解决方案

PlanAhead tool should generate an error stating that the particular DCI standard is not allowed in this particular bank.

This is a known issue and fixed in PlanAhead tool 13.2.
AR# 42475
日期 07/11/2011
状态 Active
Type 已知问题
器件
Tools
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