AR# 42483


Spartan-6 Soft Error Mitigation Controller - Component switching limit errors


Known Issue for v2.1 and later

When running the implementation tools on the SEM controller for a range of target clock frequencies, a component switching limit timing error may be reported in MAP, PAR, and TRCE.

WARNING:Pack:2768 - At least one timing constraint is impossible to meetbecause component switching limit violations have been detected for a constrained component.


This issue may be safely ignored ifTRCE indicates that this componentswitching limit error is on net "clk_IBUFG" for clock network "icap_clk",and indicates that the minimum clock period is 250 ns (4 MHz) for S6 -1L devices, 50 ns (20 MHz) for S6 LX4-LX75 devices, or 83.333 ns (12 MHz) forS6 LX100-LX150 devices.

The Spartan-6 FPGA SEM controller performs configuration readback through the ICAP excluding type 1 frames. This allows the ICAP to be clocked at ahigher rate than reported by the tools. Refer to DS162 for the maximumICAP readback frequency (F_RBCCK) ignoring block RAM.

Revision History
12/18/2012 - Updated "Known issue for v2.1 and later"
07/06/2010 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
42519 Soft Error Mitigation Controller v2.1 - Release Notes and Known Issues N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
44541 Soft Error Mitigation Controller - Release Notes and Known Issues for v1.1 to v3.4 N/A N/A
AR# 42483
日期 12/18/2012
状态 Active
Type 版本说明
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