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AR# 42559

MIG 7 Series v1.1, v1.2 DDR3 SDRAM - Additional hard block constraints are incorrectly generated when reset_n pin is moved to a different bank for a multi-controller design

描述

When I run both Verify/Update and Fixed Pin-out on a design where the reset_n pin has been moved to a different bank from the remaining interface pins, additional hard block constraints are generated for the bank the reset_n pin is assigned to. These constraints are incorrect and result in an unroutable situation during implementation.

解决方案

The reset_n pin does not require PHASER_CONTROL, OUT_FIFO, PHASER_OUT, and PHASER_REF. Therefore, the following must be performed to work around the problem:

If reset_n is allocated a bank below Data and Address/Control byte groups:

  • Remove the additional constraints from the UCF.
  • Set the BYTE_LANES_B# parameter to 0 for the reset_n allocated byte group.In this situation, MIG treats reset_n as a pin allocated in the Address/Control byte group, and sets up BYTE_LANES_B# and DATA_CTL_B# accordingly.

If reset_n is allocated a bank above Data and Address/Control byte groups:

  • Remove the additional constraints from the UCF.
  • Set the BYTE_LANES_B# parameter to 0 for the reset_n allocated byte group.
  • Move all BYTE_LANES_B# lanes up to the next BYTE_LANES_B#. For example, shift all BYTE_LANES_B1 to BYTE_LANES_B0. The bank location also needs to be updated for all the *_MAP parameters.
Example:
ADDR_MAP= 192'h000_000_139_138_137_136_135_134_133_132_131_129_128_127_126_12B,

Change to:
ADDR_MAP= 192'h000_000_039_038_037_036_035_034_033_032_031_029_028_027_026_02B,

    This problem does not affect single controller designs as these constraintsare automatically trimmed away by the ISE software.This issue is scheduled to be fixed in the 13.3 software release and further documentation on the pin-out parameters is to be provided.

    链接问答记录

    主要问答记录

    Answer Number 问答标题 问题版本 已解决问题的版本
    40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

    相关答复记录

    AR# 42559
    日期 05/20/2012
    状态 Active
    Type 已知问题
    器件
    • Artix-7
    • Kintex-7
    • Virtex-7
    • Virtex-7 HT
    IP
    • MIG
    的页面