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AR# 42665

MIG 7 Series - Why does the MIG Example Design fail in BitGen?

描述

When I generate a bitstream for a MIG 7 Series Example Design, the following error message occurs:

"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD).This maycause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow."

解决方案

This error message occurs when generating the bitstream for the MIG 7 Series Example Design when one or all of the system and status signals internally. If any of the pins are left as "No connect", the ISE tools select the pins as needed in the implementation phase.

For more information about the error message and how to downgrade this to a warning message, please refer to(Xilinx Answer 41615).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
46227 MIG 7 Series Solution Center - Top Issues N/A N/A

相关答复记录

AR# 42665
日期 12/15/2012
状态 Active
Type 综合文章
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series
的页面