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AR# 42678

13.2 Bitgen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"


For the 7 Series family, bitgen will issue an error message if there are any I/Os that do not have pin constraints or have an undefined I/O Standard. See Xilinx (Xilinx Answer 41615) for further details.

This error message erroneously occurs when there is a differential pair and the P-side has a LOC and IOSTANDARD constraint.


This is a bug in software and will be fixed in a future software version. To work around, the user can define the LOC and IOSTANDARD for the N-side of the differential pair.

NOTE: If you use PlanAhead tool to define the P-side LOC and IOSTANDARD constraints, the tool will automatically write the N-side LOC and IOSTANDARD constraints.



AR# 42678
日期 12/15/2012
状态 Active
Type 综合文章
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT