UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42725

MIG 7 Series v1.2 - No CC pair available for System Clock

描述

Why do I receive the following error during the Bank Selection of my controller?

"Error: CC pair is reserved in the Byte group T3 of Bank 33 for System Clock. Deselect"

解决方案

This can affect designs that only have two banks in a column and require 4 Address/Control byte groups as the System Clock must be placed in the same bank as Address/Control. However, the Address/Control pins are occupying all the CC pins so there are none available to place the differential System Clock pins.

This can be worked around by allocating the Address/Control byte groups more efficiently. Such as moving Address/Control-3 from its default locations Byte Group T3 to T1 or T2 Byte Group to free up a CC pair for System Clock in T3 Byte Group.

This will be automatically done by default for users starting in the 13.3 software release.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A

相关答复记录

AR# 42725
日期 05/23/2014
状态 Archive
Type 已知问题
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG
的页面