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AR# 42730

MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo instantiation file

描述

Why is the CLK_STABLE parameter in the Verilog .VEO instantiation file set to %CLK_STABLE?

解决方案

This is a known issue with the MIG v1.1-v1.2 QDRII+ *.VEO instantiation file as the CLK_STABLE parameter should be set to the number of cycles to wait until the echo clocks are stable. This value is dependent on the memory vendor's data sheet but is set to 2048 by default.

This will be fixed in the ISE 13.3 software release but can be worked around by setting the value of the CLK_STABLE parameter manually in the .VEO instantiation file.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A

相关答复记录

AR# 42730
日期 05/26/2014
状态 Archive
Type 已知问题
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG
的页面