AR# 42730: MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo instantiation file
MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo instantiation file
Why is the CLK_STABLE parameter in the Verilog .VEO instantiation file set to %CLK_STABLE?
This is a known issue with the MIG v1.1-v1.2 QDRII+ *.VEO instantiation file as the CLK_STABLE parameter should be set to the number of cycles to wait until the echo clocks are stable. This value is dependent on the memory vendor's data sheet but is set to 2048 by default.
This will be fixed in the ISE 13.3 software release but can be worked around by setting the value of the CLK_STABLE parameter manually in the .VEO instantiation file.