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AR# 4278

M1.4 PAR - FPGA Express 2.1.1 designs with incomplete RLOC specifications fail in PAR.

Description

Cases have been seen where FPGA Express 2.1.1 creates loadable
counters that only have the first and last registers RLOC'd.
As a result the M1 mapper creates an RPM macro that contains
only the first and last CLBs of the carry chain. The rest of
the counter logic is mapped into individual CLBs. PAR is
unable to handle placement of a carry chain that is a mixture
of a macro and independent CLBs and fails with the error:

ERROR:x4kpl - RPM "inc_rpl_8_9_2" contains a partial carry
logic chain. This is not supported in the current release.
Carry logic chains must either be fully contained in the RPM
or not in an RPM at all. The carry logic chain is broken at
CLB "N138" and is driven by CLB "N93" which is not contained
in this RPM.

解决方案

This problem can be worked around by either completing
the RLOC specifications for the middle registers in the
.ucf file (1) or by canceling the RLOC specifications for
the end registers in the .ucf file (2). PAR will successfully
place the carry chain either way.

(1) The following constraints fix a counter that already
has INST QOUT_reg<0> and INST QOUT_reg<7> RLOC'd by
FPGA Express:

INST QOUT_reg<1> HU_SET=inc_rpl_8_9_2 ;
INST QOUT_reg<2> HU_SET=inc_rpl_8_9_2 ;
INST QOUT_reg<3> HU_SET=inc_rpl_8_9_2 ;
INST QOUT_reg<4> HU_SET=inc_rpl_8_9_2 ;
INST QOUT_reg<5> HU_SET=inc_rpl_8_9_2 ;
INST QOUT_reg<6> HU_SET=inc_rpl_8_9_2 ;
INST QOUT_reg<1> RLOC=R4C0.FFX ;
INST QOUT_reg<2> RLOC=R3C0.FFY ;
INST QOUT_reg<3> RLOC=R3C0.FFX ;
INST QOUT_reg<4> RLOC=R2C0.FFY ;
INST QOUT_reg<5> RLOC=R2C0.FFX ;
INST QOUT_reg<6> RLOC=R1C0.FFY ;

(2) The following constraints cancel the RLOC attributes
on INST QOUT_reg<0> and INST QOUT_reg<7>:

INST QOUT_reg<0> use_rloc=false ;
INST QOUT_reg<7> use_rloc=false ;

(3) This problem can be worked around without re-mapping by
unbinding the partial macro in EPIC.

AR# 4278
创建日期 07/17/1998
Last Updated 04/03/2000
状态 Archive
Type 综合文章