AR# 42809


7 Series FPGAs Transceiver Wizard v1.4 - Known Issues and Release Notes


This Answer Record contains the Known Issues and Release Notes for the 7 Series FPGAs Transceiver Wizard v1.4 released with ISE 13.2 software.



For installation instructions for this release, please go to:

For system requirements, go to:

This file contains release notes for the Xilinx LogiCORE IP 7 Series FPGAs
Transceivers Wizard v1.4 solution. For the latest core updates, see the product page at:

New Features

  • ISE 13.2 software support
  • Support for non-identical line rates for TX and RX
  • Support for protocols - Aurora 8B/10B, Aurora 64B/66B, OBSAI, SRIO GEN1, SRIO GEN2, OC48, OC192
  • ChipScope support

Supported Devices

The following device families are supported by the core for this release.

  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2L

Resolved Issues

  • CR # 603156 - Updated RXBUF_ADDR_MODE setting for Interlaken protocol.
  • CR # 603158 - Changed Source for RXUSRCLK to RXOUTCLK, 'Synchronous Application" to OFF for Interlaken protocol template.
  • CR # 606028 - Updated the maximum line rate supported by Kintex-7 FBG or SBG packages to 6.6 Gb/s for all speed grades.
  • CR # 608819 - Fixed issues in the calculation of TXOUT_DIV and RXOUT_DIV.
  • CR # 593469 - Updated the calculation of CLK_COR_MIN_LAT and CLK_COR_MAX_LAT attributes.

Known Issues

The following are known issues for v1.4 of this core at time of release:

  • Hardware Validation has not been carried out for this release of the core.
  • ChipScope feature has not been tested on hardware
  • While importing an ISE project from PlanAhead tool with "Import sources to the project directory" option enabled, the implementation is not successful. To workaround this issue, either user has to uncheck the "Import sources to project directory" option from PlanAhead GUI or manually copy the BRAM initialization <>.dat files to PlanAhead project area where the associated RTL files are located.
  • XST synthesis constraint <core>.xcf support is not available in "Project Navigator" tool. To import the ISE project (generated by the wizard) in GUI mode, please migrate to PlanAhead and manually add <core_top>.xcf to current workspace in GUI mode after importing the ISE based <core>.xise file.

The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide.

Technical Support

To obtain technical support, create a WebCase at Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

Other Information

  • None

Core Release History

 Date        By            Version      Description
 06/22/2011  Xilinx, Inc.  1.4          13.2 Release
 03/01/2011  Xilinx, Inc.  1.3          13.1 Release
 11/23/2010  Xilinx, Inc.  1.2          ISE 7 Series Beta2 - (O.34)
 10/29/2010  Xilinx, Inc.  1.1          ISE 7 Series Monthly Snapshot - (O.28)
                                         Initial release



Answer Number 问答标题 问题版本 已解决问题的版本
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
AR# 42809
日期 11/10/2014
状态 Active
Type 综合文章
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