AR# 42836: MIG 7 Series v1.2 - Incorrect Phaser IN and PHASER OUT Constraints Generated for Compatible Artix-7 Device
MIG 7 Series v1.2 - Incorrect Phaser IN and PHASER OUT Constraints Generated for Compatible Artix-7 Device
The MIG 7 Series v1.2 PHASER_IN and PHASER_OUT constraints are generated incorrectly for the compatible device xc7a50t-csg324 when targeting the xc7a100t-csg324 device for core generation. This issue exists if the banks 35 and 34 are selected for Data and Address/Control byte groups. There is no issue if the banks are selected as memory banks.
To work around the issue, generate the MIG 7 Series v1.2 design with the target device as xc7a50t-csg324 instead of selecting it as a compatible device.