AR# 42882

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SPI-4.2 v10.4 - Timing errors encountered when using the 128-bit client interface

描述

In the SPI 4.2 v10.4 and earlier core, occasionally timing errors can be seen when using the example design constraints and a 128-bit user interface.

解决方案

The example UCF constraints over-constrains this interface at the full internal core clock rate.  Switching all 128-bit user interface clock constraints to be 3/4 of the internal core clock resolves this issue. The UCF constraints have been updated in v10.5 and later of the SPI 4.2 core.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40638 SPI-4.2 v10.4 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
42572 SPI-4.2 v10.5 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
AR# 42882
日期 05/23/2014
状态 Archive
Type 综合文章
IP
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