AR# 43097

Virtex-6 FPGA Connectivity Kit TRD - The PlanAhead Flow on a 32-bit OS Does Not Meet Timing

描述

The PlanAhead flow on 32-bit operating systems(both Windows and Linux) does not meet timing on the cost table set in the tcl script.

解决方案

For x4gen2:

Open the tcl file planahead_flow_x4gen2.tcl available in v6_pcie_10Gdma_ddr3_xaui_axi/design/implement/planahead_flow_x4gen2 directory.

Change the cost table in the following lines from 3 to 10:

config_run -run impl_1 -program map -option -t -value 3
config_run -run impl_1 -program par -option -t -value 3

For x8gen1:

Open the tcl file planahead_flow_x8gen1.tcl available in v6_pcie_10Gdma_ddr3_xaui_axi/design/implement/planahead_flow_x8gen1 directory.

Change the cost table in the following lines from 3 to 6:

config_run -run impl_1 -program map -option -t -value 3
config_run -run impl_1 -program par -option -t -value 3

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34432 Virtex-6 FPGA Connectivity Kit and Targeted Reference Design (TRD) - Release Notes and Known Issues N/A N/A
AR# 43097
日期 05/20/2012
状态 Archive
Type 已知问题
Boards & Kits