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AR# 4313

14.x Timing - What are the design statistics in the timing summary (i.e., maximum/minimum arrival input/output time)?

Description

There is a timing summary at the bottom of the timing report. What do the design statistics in this summary mean?

解决方案

Design Summary

Minimum Period
The maximum delay from any synchronous element to another; displayed in MHz. These paths can run at this frequency.

Maximum path delay from/to any node
The maximum delay from any node to any other node.

Minimum input arrival time before clock
The minimum global OFFSET IN BEFORE.

Maximum input arrival time after clock
The maximum global OFFSET IN AFTER.

Minimum output arrival time before clock
The minimum global OFFSET OUT BEFORE.

Maximum output arrival time after clock
The maximum global OFFSET OUT AFTER.

For more information, see (Xilinx Answer 7013) and (Xilinx Answer 6501).
AR# 4313
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
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  • ISE Design Suite - 11.3
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  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
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