AR# 43130

描述

This Release Notes and Known Issues Answer Record is for the Memory Interface (MIG) v3.9 release in the ISE Design Suite 13.3 and contains the following information:

• General Information
• Software Requirements
• New Features
• Resolved Issues
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

解决方案

General Information

The MIG Virtex-6 and Spartan-6 v3.9 products are available through the ISE Design Suite 13.3. 

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA Memory Controller Block (MCB), see the following user guides:

• Spartan-6 FPGA Memory Controller User Guide (UG388)
• Memory Interface Solutions User Guide (UG416)

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the following documentation:

• Virtex-6 FPGA Memory Interface Solutions User Guide (UG406)
• Virtex-6 FPGA Memory Interface Solutions Data Sheet (DS186)

For general design and troubleshooting information on MIG, see the Xilinx MIG Solution Center at (Xilinx Answer 34243)

Software Requirements

• Xilinx ISE Design Suite 13.3
• 32-bit/64-bit Windows XP Professional
• 32-bit/64-bit Windows 7 Professional
• 32-bit/64-bit Windows Server 2008
• 32-bit/64-bit Linux Red Hat Enterprise 4.0
• 32-bit/64-bit Linux Red Hat Enterprise 5.0
• 32-bit/64-bit SUSE Linux Enterprise 11

New Features

• ISE Design Suite 13.3 software support

Resolved Issues

• MIG User Guide

  • UG406 - Added more information in AXI addressing section

    • CR590370
  • UG416 - Added more information in the Debug Signals section
    • CR576956
• MIG Tool
  • Arbitration algorithm selection is added for AXI interface designs of DDR3 SDRAM and DDR2 SDRAM
  • CR616189
• Virtex-6

• (Xilinx Answer 35750) MIG v3.4-v3.8 Virtex-6 QDRII+ - Why is the QVLD signal left unconnected?

  • CR560728
• Added support for part "MT47H128M16RT-25E" of DDR2 SDRAM
•        CR5614623

• Arbitration algorithm parameter (C_RD_WR_ARB_ALGORITHM) added for AXI interface designs of DDR3 SDRAM and DDR2 SDRAM
  • CR616189
• Fixed RTL logic issue in DDR3 SDRAM dual rank VHDL designs
  • CR616399
• (Xilinx Answer 41653) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator address data masking is inconsistent in cmd_gen.vhd
  • CR605211
• (Xilinx Answer 41918) MIG v3.7-v3.8 Virtex-6 DDR2/DDR3 - Traffic Generator does not simulate other data or command patterns
  • CR607737, CR607735, CR607734
• (Xilinx Answer 41652) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator error_status does not latch correct data
  • CR605210
• (Xilinx Answer 42827) MIG v3.8 Virtex-6 QDRII+ - ChipScope cores are not detected in the JTAG device chain
  • CR614912
• Spartan-6

  • Custom part selection range for Row Address is restricted to a maximum value of 15 for DDR3 SDRAM, which is the same as the MCB allowed maximum value

    • CR603432
  • Added support for new memory parts for DDR3 SDRAM designs.
    • CR615075, CR620948
  • (Xilinx Answer 42829) MIG 3.8 Spartan-6 MCB - Custom part for MCB allows ranges that exceed the supported address space.
    • CR603432

Known Issues

• Virtex-6 FPGA MIG Designs
  • (Xilinx Answer 38731) MIG v3.5-v3.9, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design
  • (Xilinx Answer 39423) MIG v3.6-v3.9 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/O's which require another bank for DCI Cascade
  • (Xilinx Answer 44329) MIG v3.9 Virtex-6 DDR3/DDR2 - AXI Designs are failing in ModelSim with a Segmentation Fault
• Spartan-6 FPGA MIG Designs
  • (Xilinx Answer 38623) MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mb/s?

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