AR# 43185

MIG 7 Series - Requirement of System Clock Input


The system clock input is used to create all MIG design clocks thatclock the internal logic, the phasers, and PHY control blocks. The system clock input for the memory interface is typically connected to a low-jitter external clock source. Either a single input or a differential pair can be selected based on the System Clock selection in the FPGA Options page in the MIG tool.


The system clock input must be in the same column as the memory interface, which should be allocated to either a Single Region Clock Capable (SRCC) I/O pair or a Multi-Region Clock Capable (MRCC) I/O pair. If this pin is connected in the same banks as the memory interface, the MIG tool selects an I/O standard compatible with the interface, such as DIFF_SSTL15 or SSTL15. If sys_clk is not connected in a memory interface bank, the MIG tool selects an appropriate standard such as LVCMOS18 or LVDS. The UCF can be modified as desired after memory controller generation.

For more information on clocking guidelines and the sharing ofsys_clk between controllers, please refer to theMIG 7 Series DDR3/DDR2 Clocking Guidelines(Xilinx Answer 40603).



Answer Number 问答标题 问题版本 已解决问题的版本
40603 MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines N/A N/A
AR# 43185
日期 02/20/2013
状态 Active
Type 综合文章