It is possible, however, the electrical characteristics of the Sub-LVDS input need to be checked to ensure that it meets the Spartan-6 FPGAinput requirements.
Take the following Sub-LVDS specifications:
|Fixed common mode voltage VCMF||0.8||0.9||1.0||V|
|Differential voltage swing VOD||100||150||200||mV|
|Drive current range||0.833||1.5||2||mA|
In the case above the Standard LVDS input buffer can be used:
For the input swing VID Min/ Max 100mV / 600mV the Sub-LVDS is 100 / 200mV; so, this is within spec.
The LVDS common mode it is 0.3mV -> 2.35V and the Sub-LVDS is 0.8mV -> 1V; which is also within spec.
The normal LVDS termination can be used. However, an IBIS simulation should be done in all cases to ensure the signal integrity is correct.