In the 13.3 software release, MIG 7 Series v1.3 has made changes to some of the bank selection rules. These changes are listed as follows:
- All Address/Control groups should be in the same bank. This applies to all interfaces.
- (Xilinx Answer 41981)MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Cntrl Pins Should be Limited to a Single Bank
- Address/Control should be in the middle bank when an interface spans across 3 banks. This is applicable to DDR3 SDRAM and RLDRAM II.
- Banks must be selected continuously. This applies across all interfaces.
- Address/Control should be adjacent to Data Write bank. This is applicable to QDRII+ SRAM.
The "Verify Pin Changes and Update Design" flow might error out with a PRJ and UCF file created prior to MIG 7 Series v1.3 if the new rules have been violated. The new bank selection rules are scheduled to be updated in MIG 7 Series v1.4.
If these new rules must be avoided, please contact Xilinx Technical Supportfor assistance.