AR# 4354


4.2i Foundation - I am unable to synthesize or add an ABEL file to an HDL project


Keywords: ABEL, HDL, synthesize, top level, grayed out, not highlighted

Urgency: Standard

General Description:
I cannot add an ABEL file to my project in Project Manager, and the "ABEL" language selection is grayed out.



If you wish to create a top-level ABEL design, you must do this in a "Schematic" project flow.

Please see (Xilinx Answer 4353) for more information on this process.


If you wish to include an ABEL file in a top-level VHDL or Verilog design, you must instantiate the ABEL module as a black-box in the VHDL or Verilog.

First, the ABEL file must be synthesized to an EDIF file; this EDIF file is then instantiated as the black box in the top-level VHDL or Verilog.
AR# 4354
日期 08/12/2003
状态 Archive
Type 综合文章
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