AR# 43540

描述

When calibration fails or data/bit errors occur in hardware, it might be necessary to determine whether the issue is related to the write or read.This answer record focuses on how to determine whether the write or read is the root cause of the issue at hand.

This answer record is contained in a series of MIG hardware debug answer records and assumes you are running the MIG Example Design with the Debug Port Enabled. It is best to start at the beginning of this recommended hardware debug flow; see (Xilinx Answer 43520).

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Isolating whether data corruption is due to writes or reads can be difficult to determine because if writes are the cause, read back of the data is bad as well. In addition, issues with control or address timing affect both writes and reads.

A few experiments that can be performed to isolate the issue:

• If the errors are intermittent, have the controller issue a small initial number of writes, followed by continuous reads from those locations. If the reads intermittently yield bad data, there is a potential read problem.
• Check/vary Output Termination:
  • Select OUT_TERM=UNTUNED_25 or OUT_TERM=UNTUNED_50. Refer to (Xilinx Answer 41721).
• Check/Vary Input Timing/Termination:
  • If on-die termination is used, check that the correct value is enabled in the DDR2/DDR3 device and that the timing on the ODT signal relative to the write burst is correct.
  • By default, MIG delays the DQS by 3/8 of a bit period with respect to DQ. This value was found to provide the best capture window through extensive characterization. However, if your design uses different termination schemes than have been characterized, using a different delay might provide more reliable data capture.To change the DQS delay, see(Xilinx Answer 43643).