AR# 43845

Spartan-6 FPGA SP601 Evaluation Kit - Interface Test Designs


I am attempting to exercise the interfaces on the Spartan-6 FPGA SP601 Evaluation Kit.

What tests can be run to ensure that the interfaces are working correctly?


Spartan-6 FPGA SP601 Evaluation Kit Documentation and Reference Designs referenced below can be found on the SP601 Support page.

FeatureTest Design


Configuration Interfaces
Configuration Mode SwitchesSP601 BIST (XTP041)Page 17
Configuration USB JTAG portSP601 BIST (XTP041)Page 35
Configuration BPI FlashSP601 BIST (XTP041)Page 47
Configuration SPI FlashMultiBoot Design (XTP038)Page 9
Board Feature Interfaces
Board DDR2 MemorySP601 BIST (XTP041)Page 26
Board I2C InterfaceSP601 BIST (XTP041)Page 22
Board RJ45 - Ethernet PHYSP601 BIST (XTP041)Page 24
Board USB Serial UARTSP601 BIST (XTP041)Page 18
Board Digilent 2x6 headerStandalone Apps (XTP053)Page 21
Board FMC-LPC connectorXM105 User Guide (UG537)Page 29. This is the User Guide for the XM105 mezzanine debug card.
This card has DS5, DS6, and DS7 which indicate good power to the board.
Debug strategies will vary depending on the specific mezzanine card being used.
User Specified Interfaces
User LEDsSP601 BIST (XTP041)Page 20
User DIP SwitchesSP601 BIST (XTP041)Page 25
User PushbuttonsSP601 BIST (XTP041)Page 25
User SMA CLK Connectors (differential)none availableThese are completely user-driven I/O. A good test would be loop back or monitoring differential I/O on a scope.
User CLK Socket ConnectorMultiBoot Design (XTP038)Any of these designs will exercise the clock. If they work, the CLK socket is working as expected.




Answer Number 问答标题 问题版本 已解决问题的版本
43748 Xilinx Boards and Kits - Debug Assistant N/A N/A
AR# 43845
日期 07/05/2018
状态 Active
Type 综合文章
Boards & Kits