AR# 4392


FPGA Express - Attribute passing is available beginning with version 3.0


Keywords: Foundation Express, FPGA Express, VHDL, Verilog, attribute, INIT, RAM, ROM, initialize

Urgency: Standard

General Description:
As of FPGA Express 3.0, attributes may be inserted in the HDL code to be passed on to the resulting netlist. These attributes can have any name or value, but they can only be applied to instantiated components or nets (not inferred logic or ports). Earlier versions of Express do not support any attribute passing.

The version of Foundation Express that is included with F1.5i Service Pack 1
(FPGA Express 3.1) supports attribute passing.

Use the syntax below to place an attribute in your HDL.




Place the following in the architecture before the "begin" keyword:

attribute <name> : string;
attribute <name> of <instance> : label is <value>;

The second attribute is applied to the instance name of an instantiation.
If applying an attribute to a signal instead of a component, replace "label" with "signal".

For example:

attribute LOC: string;
attribute LOC of CLOCKBUF: label is "BR";
CLOCKBUF:BUFG port map(I=>oscout,O=>clkint);

If multiple attributes need to be applied to the same component, simply
create two lines for each attribute:

attribute INIT_00: string;
attribute INIT_00 of MY_BLKRAM: label is "AAAAAAAAAAAAAAAA";
attribute INIT_09: string;
attribute INIT_09 of MY_BLKRAM: label is "9999998888888888";

MY_BLKRAM : RAMB4_S4 port map (
addr => ADDRTWO,
di => DINTWO,
clk => CLK,
we => WETWO,
en => ENTWO,
rst => RST,
do => DOUTTWO);



//synopsys attribute <name> <value>

This comment is placed immediately after the instantiated component

For example:

BUFG CLOCKB (.I(oscout), .O(clkint)); //synopsys attribute LOC "BR"

If multiple attributes need to be applied to the same component, use
multi-line comments, like so:

RAMB4_S4 U1 (.WE(w), .EN(en), .RST(r), .CLK(ck), .ADDR(ad), .DI(di), .DO(do));
INIT_09 "99999988888888887777777776666666" */
AR# 4392
日期 08/11/2003
状态 Archive
Type 综合文章
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