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AR# 44012

7 Series Integrated Wrapper for LogiCORE CPRI - TXOUTCLK and RXOUTCLK Port Restrictions

描述

There are some restrictions in using the TXOUTCLK and RXOUTCLK ports for the Initial Engineering Sample (ES) silicon.As a result, you need to update your instantiations to account for these restrictions.For more information, please see (Xilinx Answer 43244).

解决方案

This article describes the restrictions on the TXOUTCLK and RXOUTCLK ports of the transceiver. To cope with these restrictions, the MMCM transmitter input now comes from the reference clock, IBUFDS_GTE2. And, the transceiver TXOUTCLK port is disabled. The receiver side clocking remains unchanged. You must also set the TXOUTCLKSEL input to the GTXE2_CHANNEL instance to "000".

  1. Change the input to the k7_bufg_gen BUFG component in the <component_name>/example_design/gtx_and_clocks/gt_and_clocks.vhd file: k7_bufg_gen : BUFG port map (I => refclk, O => txoutclk_bufg);
  2. Route the BUFG output to the refclk input of the tx_clk_gen instance.
  3. Leave the GT0_TXOUTCLK_OUT port of the GTWIZARD instance open:
    GT0_TXOUTCLK_OUT => open,

Figure 1 shows the revised clocking scheme.

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For the LogiCORE CPRI Release Notes and Known Issues, see (Xilinx Answer 36969).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
36969 LogiCORE IP CPRI - Release Notes and Known Issues N/A N/A

相关答复记录

AR# 44012
日期 05/22/2012
状态 Archive
Type 已知问题
IP
  • CPRI
的页面