AR# 4407: FPGA Express: leaving pins open on VHDL component instantiations (VSS-538, VSS-544)
FPGA Express: leaving pins open on VHDL component instantiations (VSS-538, VSS-544)
Keywords: FPGA, Express, VHDL, instantiate
General Description: When a black box is instantiated in VHDL code, all declared pins must be accounted for. This becomes a problem if a component is declared with all its pins but only some are needed, or if a component is instantiated multiple times are different pins are used each time.
If pins are left unconnected, FPGA Express returns this error:
Error: C:/designs/top.vhd line 53 Not enough element associations - 3 expected. (VSS-538) (FPGA-dm-hdlc-unknown)
If the keyword "open" is used to leave declared pins unconnected, FPGA Express returns this error:
Error: C:/designs/top.vhd line 55 OPEN is not a legal actual part of an element association here (check if the input ports are properly mapped). (VSS-544) (FPGA-dm-hdlc-unknown)
When declaring the component, assign initial values to any pins that may be left unconnected when instantiated. These values will not be used in synthesis, as these ports will either be connected to valid signals or left unconnected entirely. Then, at the component instantiation, use the "open" keyword to denote unconnected ports.
... component STARTUP_VIRTEX port ( GSR: in STD_LOGIC; GTS: in STD_LOGIC := '1'; -- initial values defined CLK: in STD_LOGIC := '1'); end component;
mystart : STARTUP_VIRTEX port map ( GSR => RST, GTS => open, --open keyword used to leave pin unconnected CLK => open); ...