AR# 44215

描述

解决方案

To enable the transceiver transmit and receive elastic buffers:

• Set RXBUF_EN to "TRUE" in the <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard_gt.vhd file.
• Set TXBUF_EN to "TRUE" in the <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard_gt.vhd file.
• In the same file, set RX_XCLK_SEL to "RXREC" .
• In the same file, set TX_XCLK_SEL to "TXOUT".
• In addition, disable the transmit and receive phase alignment.

Set the RX Elastic Buffer and Phase Alignment Ports section of <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard_gt.vhd to:

-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------

RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXDDIEN => tied_to_ground_i,
RXDLYBYPASS => tied_to_vcc_i,
RXDLYEN => tied_to_ground_i,
RXDLYOVRDEN => tied_to_ground_i,
RXDLYSRESET => tied_to_ground_i,
RXDLYSRESETDONE => open,
RXPHALIGN => tied_to_ground_i,
RXPHALIGNDONE => open,
RXPHALIGNEN => tied_to_ground_i,
RXPHDLYPD => tied_to_ground_i,
RXPHDLYRESET => tied_to_ground_i,
RXPHMONITOR => open,
RXPHOVRDEN => tied_to_ground_i,
RXPHSLIPMONITOR => open,
RXSTATUS => open,

Set the TX Elastic Buffer and Phase Alignment Ports section of the same file to:

----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------

TXBUFSTATUS => open,
TXDLYBYPASS => tied_to_vcc_i,
TXDLYEN => tied_to_ground_i,
TXDLYHOLD => tied_to_ground_i,
TXDLYOVRDEN => tied_to_ground_i,
TXDLYSRESET => tied_to_ground_i,
TXDLYSRESETDONE => open,

For more information, see the LogiCORE CPRI Release Notes and Known Issues (Xilinx Answer 36969).

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