To enable the transceiver transmit and receive elastic buffers:
Set the RX Elastic Buffer and Phase Alignment Ports section of <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard_gt.vhd to:
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXDDIEN => tied_to_ground_i,
RXDLYBYPASS => tied_to_vcc_i,
RXDLYEN => tied_to_ground_i,
RXDLYOVRDEN => tied_to_ground_i,
RXDLYSRESET => tied_to_ground_i,
RXDLYSRESETDONE => open,
RXPHALIGN => tied_to_ground_i,
RXPHALIGNDONE => open,
RXPHALIGNEN => tied_to_ground_i,
RXPHDLYPD => tied_to_ground_i,
RXPHDLYRESET => tied_to_ground_i,
RXPHMONITOR => open,
RXPHOVRDEN => tied_to_ground_i,
RXPHSLIPMONITOR => open,
RXSTATUS => open,
Set the TX Elastic Buffer and Phase Alignment Ports section of the same file to:
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => open,
TXDLYBYPASS => tied_to_vcc_i,
TXDLYEN => tied_to_ground_i,
TXDLYHOLD => tied_to_ground_i,
TXDLYOVRDEN => tied_to_ground_i,
TXDLYSRESET => tied_to_ground_i,
TXDLYSRESETDONE => open,
For more information, see the LogiCORE CPRI Release Notes and Known Issues (Xilinx Answer 36969).
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
36969 | LogiCORE IP CPRI - Release Notes and Known Issues | N/A | N/A |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
43244 | 面向 Kintex-7 和 Virtex-7 FPGA GTX 收发器的设计咨询 - 用于初始工程样片 (ES) 芯片的属性更新、问题和解决方案 | N/A | N/A |
44010 | 7 Series Integrated Wrapper for LogiCORE CPRI - GTXE2_COMMON Use Model Change | N/A | N/A |
44011 | 7 Series Integrated Wrapper for LogiCORE CPRI - IBUFDS_GTE2 Use Model Change | N/A | N/A |
44012 | 7 Series Integrated Wrapper for LogiCORE CPRI - TXOUTCLK and RXOUTCLK Port Restrictions | N/A | N/A |
43339 | 7 Series FPGA GTX Transceiver - Software Use Model Changes | N/A | N/A |
AR# 44215 | |
---|---|
日期 | 08/28/2012 |
状态 | Archive |
Type | 已知问题 |
IP |