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For all devices, Xilinx specifies worst-case delays. These worst-case delays are used to populate all three delay fields in the SDF file.
For certain devices, absolute minimum delays are also specified. If minimum delays are available for a device, NGDAnno can be run with the "-s min" option. When the "-s min" option is used, all three delay fields will contain the absolute minimum delays. For more information on minimum delays, see (Xilinx Answer 4506).
To create an SDF file that contains minimum delays, run the following commands (you cannot run these commands from the GUI; this will be fixed in the next major software release):
1. Type the following:
ngdanno [other options] -s min design.ncd
2. For VHDL, type:
ngd2vhdl [options] design.nga
For Verilog, type:
ngd2ver [options] design.nga
The minimum delays apply to all device speed grades, and Xilinx does not recommend that you use them in a worst-case analysis (i.e., setup, min clock, max data). These minimum speed files allow you to check timing between chips on a board.
A minimum delay is a calculation of 25% faster than the fastest planned speed grade for a device. (Given the fastest planned speed grade for a device, the minimum speed file is created by taking 75% of each delay from that file.) Therefore, these minimums are specific to a device, not to the speed grade or the PVT variation across a single piece of silicon.
These minimum speed grades are intended to assist in verification of chip-to-chip timing, and not worst-case analysis. For this reason, Xilinx does not include both the minimum and maximum values in one SDF file.