MIG Spartan-6 FPGA DDR2/DDR3 - Update Design and UCF
The MIG Virtex-6 FPGAand Spartan-6 FPGAtool includes an "Update Design and UCF " option under "MIG Output Options," which allows Spartan-6 FPGAMCB designs to be updated.This feature allows you to verify changes made to a MIG output UCF, create a new design based on the verified UCF changes, and generate an updated version of the MIG core.
Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
To use the feature, input the design's mig.prj and targetUCF files. The tool will then verify theUCF based on the mig.prj settings and generate an updated design. The generated design will be updated from the version noted in the "mig.prj" to the version of MIG launched. This allows you the ability to easily update a MIG core to the newest version by simply inputting their "mig.prj" and UCF file. With this, you do not have to manually select all core options and regenerate their core to the latest version. Additionally, if any changes are made to the originally generated UCF, the tool will verify the changes and include the appropriate constraints andRTL parameters and code in the newly updated design.