AR# 44341

描述

解决方案

This issue only occurs for x18 parts when manual bank selection is done and not all the data byte groups are placed into the same bank. This can happen with x18 components with a data width of 36 and with single controller and multi-controller designs as well. There is no issue with x36 parts as all the data byte groups are placed within a single bank.

The following two scenarios will cause the incorrect MAP and UCF constraints to be generated:

Scenario #1:

By default, MIG always places Data and Data Write Clock in the same byte groups, that is, T0 and T1 byte groups. If the user selects the data byte groups as T1 and T2, then Write Clock (DK) will be allocated in T0 or T3 byte groups. MIG is then not generating PHASER_OUT and OUT_FIFO constraints for write clock which leads to routing issues. 

Scenario #2:

By default, MIG generates Data Mask (DM) pin in a Data byte group only. If the Data Mask (DM) pin is moved to a separate byte group where no other pin is allocated, then MIG is not generating the PHASER_OUT and OUT_FIFO constraints for Data Mask. This will cause failures during implementation.

This issue is scheduled to be fixed with the MIG v1.4 ISE 13.4 Design Suite release.

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