AR# 44348

MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Not Able to Proceed Past Bank Selection or System Pins Selection Page

描述

In MIG 7 Series v1.3, some Multi-Controller configurations cannot be generated and will not allow you to proceed further past the Bank Selection or System Signals selection page.

解决方案

These are valid scenarios, but the MIG 7 Series v1.3 is not providing valid messages for guidance or to indicate the problem. The following scenarios can occur:

  • If the target FPGA Device and Package is too small to fit the selected number of controllers, you cannot generate the design and will not be allowed to proceed further in the Bank Selection page. In such cases, you need to target a larger FPGA Device Package combination.
  • If there are not enough banks available to select for all controllers, then MIG will not allow youto proceed further in the Bank Selection page.In such cases, you need to target a larger FPGA Device Package combination.
  • System Clock and Reference Clock pins can only be selected for CCIO pins. If you select various banks/pins for various controllers such that there are no CCIO pins available for selection,then you cannot proceed further past the System Signals selection page. You can select the option for status signals as "No Connect" and proceed further in the design generation if you prefer.
  • "Status Signals" are not allowed in memory interface signals selected banks because of their I/O Standards are different from the memory interface signals. If all the banks are selected for memory interface signals such that there are no pins available for "Status Signals" to be placed, then you will not be able to select pins and will not be able to proceed further in the design generation.You can select the option for status signals as "No Connect" and proceed further in the design generation if you prefer.

This is scheduled to be fixed in the MIG v1.3 ISE 13.4 release.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
AR# 44348
日期 05/19/2012
状态 Active
Type 已知问题
器件
IP