AR# 44394

PlanAhead, 7 Series - What does margin in SSN analysis mean?

描述

If I am targeting a 7 Series FPGA in the PlanAhead tool and performing SSN, how is the tool analyzing the amount of noise in the system compared to the ideal margin?

解决方案

VDH (voltage drive high) - Vih min (voltage input high) =  the logic 1 ideal margin. 

Vil (voltage input low) - VDL (voltage drive low) = the logic 0 ideal margin. 

Using a hammer 101010 pattern at the resonant frequency, the noise at the far end of the line is measured for logic 1 and logic 0.

The limit is the number of I/Os that can switch and still have remaining margin. 

The remaining margin is the minimum of logic 1 ideal margin, logic1 noise, and logic 0 ideal margin, logic 0 noise.


 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
31905 Simultaneously Switching Noise - Where can I find documentation on SSO/SSN? N/A N/A

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AR# 44394
日期 07/09/2018
状态 Active
Type 综合文章
Tools