AR# 44428

描述

This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v2.2, which was released in ISE Design Suite 13.3, and includes the following:

• General Information
• New Features
• Supported Devices
• Resolved Issues
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

解决方案

General Information

• Supports automatic generation of HDL wrapper files for the Virtex-6 FPGA Tri-Mode Ethernet MAC
• Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII, and 1000Base-X PCS/PMA configurations are supported)
• Provides a FIFO-based example design
• Provides a demonstration testbench for the selected configuration
• (Xilinx Answer 33593) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Frequently Asked Questions (FAQ)

New Features

• ISE 13.3 software support
• Support for 1000BASE-X overclocking at 2 Gbps and 2.5 Gbps
• Support for Virtex-6 -1L XQ LXT/SXT devices

Supported Devices

• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Virtex-6 -1L XQ LXT/SXT

Resolved Issues

• When implemented with statistics counters - the counters are partially reset when an RX/TX soft reset is applied. The counters have been updated to only use the global reset.
  - CR 606552, (Xilinx Answer 42663)
  - This issue was fixed in the v2.1 Rev 1 patch release
• Reading the Ability register (0x4FC) always returns either 32'b1or 32'b0. The ability determination syntax has been corrected.
  - CR 612287, (Xilinx Answer 42666)
  - This issue was fixed in the v2.1 Rev 1 patch release
• SGMII or 1000BASE-X functional simulations with PHY loopback enabled donot complete, or complete with data mismatch errors. The necessarytestbench wait statements are integrated.
  - CR 591321,(Xilinx Answer 40314)
• "ERROR - Testbench timed out" for some configurations duringback-annotated timing simulations when using the Synopsys VCS simulator.
  The VCS timing simulation script is updated to prevent pulse swallowing.
  - CR 588662, (Xilinx Answer 39960)

Known Issues

• When using Virtex-6 Lower Power devices (-1L speed grade), implementationof the GMII physical interface fails to meet the receiver timing specification, and implementation of the RGMII physical interface resultsin little to no slack. (Xilinx Answer 40028)