AR# 44463


7 Series FPGAs Transceiver Wizard v1.5 - Known Issues and Release Notes


This answer record contains the Known Issues and Release Notes for the 7 Series FPGAs Transceiver Wizard v1.5 released with ISE 13.3 software.



For installation instructions for this release, see:

For system requirements, see:

This file contains release notes for the Xilinx LogiCORE IP 7 Series FPGAs Transceivers Wizard v1.5 solution.

For the latest core updates, see the Product page at:

New Features

  • ISE 13.3 software support
  • Support for Initial ES
  • Support for Timing simulation
  • Attribute Updates for Initial ES 

Supported Devices

The following device families are supported by the core for this release.

  • Virtex-7
  • Virtex-7 -2L
  • Virtex-7 -2G
  • Virtex-7 XT * (485T)
  • Kintex-7
  • Kintex-7 -2L

 *To access these devices in the ISE Design Suite, contact your Xilinx FAE.

Resolved Issues

  • Change in the value of CLKFBOUT_MULT_F generated by Wizard
    Description: Valid values for CLKFBOUT_MULT_F in MMCME2_ADV is 2 to 64.
    CR 615994
  • Check box for Channel Bonding is enabled only for 8b10b Decoding
    Description: The GTX Transceiver supports Channel Bonding only for 8b10b decoding scheme.
    CR 615993
  • Updated the Attributes RX_DFE_H4_CFG, RX_DFE_H5_CFG, Buffer Bypass
    Description: Updated the default values for these Attributes.
    CR 613574
  • Reference clock sharing restriction devices with SLRs
    Description: Reference clock cannot be shared between GTs, which reside in different SLRs.
    CR 613296
  • Change in datapath width options for 8b10b encoding
    Description: Datapath widths displayed in GUI for 8b10b encoding has been changed to 16/32/64 bits.
    CR 615652
  • Reset requirement after configuration
    Description: GTTXRESET and GTRXRESET should be asserted 500ns after the configuration is done.
    CR 621585
  • Support for Initial ES
    Description: Initial ES option has been added in the GUI for the following devices - XC7K325T (ffg676 and ffg900), XC7V485T (ffg1761, ffg1927). Initial ES is supported for -1 and -2 speed grades. Work-arounds for the following issues are implemented in the core:
    a) Attribute Updates
    b) Use Mode for Multilane Buffer Bypass
    c) Coarse Calibration Block for QPLL
    d) BIAS_CFG setting  

          For detailed information, see (Xilinx Answer 43244).


Known Issues

The following are known issues for v1.5 of this core at time of release:

  • Hardware Validation
    Description: This version of the core has been partially validated on hardware.

The most recent information, including known issues, work-arounds, and resolutions for this version is provided in the IP Release Notes Guide.

Technical Support

To obtain technical support, create a WebCase at Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

Other Information

This version of the Wizard supports Initial ES silicon only.

Use v1.6 version to program General ES devices.

For additional details, refer to (Xilinx Answer 43244).

Core Release History

Date By Version Description
01/18/2012 Xilinx. Inc. 1.5 Rev 1 ISE 13.4 software - Updates for Initial ES
10/26/2011 Xilinx. Inc. 1.5 ISE 13.3 software support
06/22/2011 Xilinx, Inc. 1.4 ISE 13.2 software support
03/01/2011 Xilinx, Inc. 1.3 ISE 13.1 software support
11/23/2010 Xilinx, Inc. 1.2 Beta 2 Release
10/29/2010 Xilinx, Inc. 1.1 Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
AR# 44463
日期 11/10/2014
状态 Active
Type 综合文章
People Also Viewed