AR# 44594: FIFO Generator v8.3 - Release Notes and Known Issues for ISE Design Suite 13.3
AR# 44594
FIFO Generator v8.3 - Release Notes and Known Issues for ISE Design Suite 13.3
描述
This Release Notes and Known Issues Answer Record is for the FIFO Generator v8.3 Core, released in the 13.3 ISE Design Suite and contains the following information:
General Information
New Features
Bug Fixes
Known Issues
Technical Support
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025).
M_ACLK mapping for write response and read data channels is corrected (CR617397)
Known Issues in v8.3
The following are known issues for v8.3 of this core at time of release:
(Xilinx Answer 31379) - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
(Xilinx Answer 41099) - When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, correct behavior of the FIFO status flags cannot be guaranteed after the first write.
Technical Support
To obtain technical support, create a WebCase. Questions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.