General Description:
In the TPTHRU dialog, the net A_EQ_B doesn't show up,
but view the design in FPGA Editor, the net is listed.
The net is connected to the CLK_EN pin (clock enable),
which is not listed under All Nets
This will be fixed in a future release of the software or
service pack.
AR# 4461 | |
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日期 | 01/18/2010 |
状态 | Archive |
Type | 综合文章 |