AR# 44625

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7 Series Integrated Block for PCI Express - VHDL simulation results in "Failure: Rx Simulation Timeout"

描述

Version Found: v1.2
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

When I run the VHDL simulation, it end with the message "Failure: RX Simulation Timeout" and the log looks like the following:

[ 127223.207 ns ] : PROC_PARSE_FRAME on Receive
Testing PIO Mem32 Space BAR 0
[ 145719.316 ns ] : PROC_PARSE_FRAME on Transmit
[ 145767.316 ns ] : PROC_PARSE_FRAME on Transmit
[ 148119.22 ns ] : PROC_PARSE_FRAME on Receive
[ 148167.23 ns ] : Test PASSED. Completion Data = 0x04030201
Failure: RX Simulation Timeout.
Time: 543655270 ps Iteration: 9 Process: /board/rp/rx_usrapp/line__1048 File: ../dsport/pci_exp_usrapp_rx.vhd
Break in Process line__1048 at ../dsport/pci_exp_usrapp_rx.vhd line 1062

解决方案

To fix this problem, edit the file named "xilinx_pcie_2_1_rport_7x.vhd" in the generated core'ssimulation/dsport/ directory.

Change:

cfg_rd_wr_done <= not cfg_rd_wr_done_n
To:
cfg_rd_wr_done_n <= not cfg_rd_wr_done

Revision History
12/06/2011 - Added version resolved reference to Answer Record 40469
10/27/2011 - Initial Release

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AR# 44625
日期 05/22/2012
状态 Active
Type 已知问题
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