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AR# 44697

MIG 7 Series - How to use DIFF_TERM_SYSCLK and DIFF_TERM_REFCLK parameters

描述

MIG allows the user to choose their desired input clock configuration as single-ended or differential. However, this selection affects both the system clock and theIDELAY control clock. In some cases, a user may wish to have separate input clock configurations for both. To do this the user must manually modify the DIFF_TERM_SYSCLK and DIFF_TERM_REFCLK in the top-level module.

解决方案

DIFF_TERM_SYSCLK defines the differential termination for System clock input pins and can be assigned to "TRUE" for differential or "FALSE" for single-ended.

DIFF_TERM_REFCLK defines the differential termination for IDELAY reference clock input pinsand can be assigned to "TRUE" for differential or "FALSE" for single-ended.
AR# 44697
日期 12/15/2012
状态 Active
Type 综合文章
器件
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
的页面