AR# 44700

AXI Bridge for PCI Express - C_PCIEBAR2AXIBAR_# restriction on bits lower than C_PCIBAR_LEN_#

描述

Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

The C_PCIEBAR2AXIBAR_# attribute describes the relationship between a BAR and the AXI memory mapped space.The address located at the BAR# registers in the configuration space is determined by the host during enumeration. The size of the BAR is determined by the C_PCIEBAR_LEN_# attribute. When a TLP is received, the address from the TLP is checked to see if it is within the BAR and BAR+2^C_PCIEBAR_LEN_#. This is determined to be a BAR hit.

Once a BAR hit is determined, the difference between the TLP address and the BAR is the offset.The offset is then appended to the C_PCIEBAR2AXIBAR_#[31:C_PCIEBAR_LEN_#] creating a total of a 32-bit range. Since C_PCIEBAR_LEN_# is a fixed value, the lower bits of C_PCIEBAR2AXIBAR_# might get stripped out depending on the value provided.

NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

解决方案

The lower bits ofC_PCIEBAR2AXIBAR_# might not get used depending on the size that waschosen forC_PCIEBAR_LEN_#. You must ensure thatC_PCIEBAR2AXIBAR_# only uses the bits from [31:C_PCIEBAR_LEN_#]. Otherwise, the lower bits will be trimmed out when concatenating with the offset.

Revision History
11/21/2011 - Updated format
10/25/2011 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 44700
日期 05/22/2012
状态 Active
Type 已知问题
IP