AR# 44706

Spartan-6 PLL - Clock phase in the INTERNAL Mode

描述

If using the Spartan-6 FPGA PLL in INTERNAL compensation mode, what is the phase relationship between the CLKIN and the CLKOUT ports?

解决方案

If you are using a PLL in the INTERNAL mode, make sure to use the PLL for frequency synthesis only. The PLL does not perform any phase-alignment or deskewing of the clock. Because of this, the phase relationship between the two clocks is not guaranteed and cannot be determined.

If the design requires that a known phase relationship be used with the PLL, use of the INTERNAL compensation mode is not recommended. In this case, use either SYSTEM_SYNCHRONOUS or SOURCE_SYNCHRONOUS, which have a known phase relationship between the input and output clock ports of the PLL.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 44706
日期 12/15/2012
状态 Active
Type 综合文章
器件