AR# 44849


ChipScope IBERT - IBERT core does not meet timing after implementation completes


This answer record provides some debugging techniques that can be used when overcoming timing issues with the ChipScope IBERT core.


In general, the ChipScope IBERT core is designed to meet timing out of the box. Since this is a less than ideal world, some designs may have difficulties meeting timing. This answer record will list some techniques that can be used to help meet timing with the IBERT core.

Change the data width of the IBERT core

Using a larger internal data width will relax timing inside the core.This is a quick and simple test that can be run that will help increase the chances that the IBERT core will meet timing

Reduce the number GT transceivers used in the IBERT design

As you add transceivers in a design, this increases the complexity of the design and makes it more and more difficult to meet timing in the IBERT core.Since IBERT is a tool that is used for testing purposes, having all GTs enabled on the device is not always necessary.This is another option that can help the IBERT core meet timing.

Run SmartXplorer on the IBERT core

This will require that you uncheck the box next to "Generate Bitstream" when you create the IBERT core.The SmartXplorer tool will allow you to run through the implementation tools with different sets of options simultaneously. More specifically, it will allow you to run through MAP with different cost tables. Use SmartXplorer to run the IBERT core through MAP using the first 10 different cost tables (-t command line option). For more information on how to use the SmartXplorer tool, see the Timing Closure User Guide (UG612).

If the ChipScope IBERT core still will not meet timing after trying the above tests, please open up a webcase with Xilinx Technical Support at:



Answer Number 问答标题 问题版本 已解决问题的版本
45201 Xilinx ChipScope Solution Center - IBERT Design Assistant N/A N/A
AR# 44849
日期 05/19/2012
状态 Active
Type 已知问题
器件 More Less
Tools More Less
IP More Less
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