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AR# 4488

EXEMPLAR, SYNPLIFY - How do I initialize a flip-flop in FPGA on power-up only? (VHDL/Verilog)

Description

Keywords: preset, set, initialize, flip-flop, flip, flop, FF, VHDL, Exemplar, register, Synplicity, Express, Exemplar init, Synplify init

Urgency: Standard

General Description:
How do I initialize a flip-flop in an FPGA on power-up only in HDL code?

(NOTE: This Answer Record is intended for 4K devices only.)

解决方案

1

If no user set is needed during operation, describe a preset/reset flop in the HDL code, then instantiate the ROCBUF that will connect to the set signal. The Xilinx tools will automatically remove the ROCBUF during implmentation (MAP).

For more information on the ROCBUF, please see (Xilinx Answer 4686).

VHDL example:

library IEEE;
use IEEE.std_logic_1164.all;

entity d_register is
port (CLK : in std_logic;
RESET : in std_logic;
D0: in std_logic;
D1: in std_logic;
Q0 : out std_logic;
Q1 : out std_logic);

end d_register;

architecture XILINX of d_register is
signal RESET_int : std_logic;

component ROCBUF is port (I : in STD_LOGIC;
O : out STD_LOGIC);
end component;


begin

U1: ROCBUF port map (I => RESET, O => RESET_int);

process (CLK, RESET_int)
begin
if RESET_int = '1' then
Q0 <= '0';
Q1 <= '1';

elsif rising_edge(CLK) then
Q0 <= D0;
Q1 <= D1;
end if;
end process;

end XILINX;

2

Verilog example:

*/NOTE: In Synplify, set the "blackbox" attribute for ROCBUF as follows:

module ROCBUF (I, O); //synthesis syn_black_box
input I;
output O;
endmodule
*/

module rocbuf_example (reset, clk, d0, d1, q0, q1) ;
input reset;
input clk ;
input d0;
input d1;
output q0 ;
output q1 ;
reg q0, q1;
wire reset_int;

ROCBUF u1 (.I(reset), .O(reset_int));

always @ (posedge clk or posedge reset_int) begin
if (reset_int) begin
q0 = 1'b0;
q1 = 1'b1;
end
else
begin
q0 = d0;
q1 = d1;
end
end
endmodule

module ROCBUF (I, O);
input I;
output O;
endmodule
AR# 4488
创建日期 08/31/2007
Last Updated 04/24/2007
状态 Archive
Type 综合文章